The present invention relates to a method and a system to accelerate address translation from a virtual address into a physical address.
In recent years, to reduce the cost of server management, virtualization techniques are actively used to integrate multiple existing servers into a single new server. When the architectures of an existing server and a new server differ from each other, the new server (also referred to as a “host” below) uses an emulator which emulates the architecture of the existing server to run the existing server (also referred to as a “guest” below) on the host. An emulator is software which enables to run a guest system on a host by emulating the architecture of the guest system. By using an emulator, guest functions can be integrated onto a host which architecture is different from the guest without recompiling the guest application.
The emulator uses a shadow page table to access data in the guest on the host based on a guest virtual address. The shadow page table manages a mapping of a guest virtual address to a host physical address, for example, by page units. Here, assume that a page unit is 4 KB. A host CPU (central processing unit) uses the shadow page table to perform automatic address translation by hardware. Most CPUs have hardware TLBs (translation lookaside buffers) to cache the results of address translation. When a virtual address hits on the hardware TLB, the address can be translated without expensive translation using the shadow page table.
Meanwhile, an increased memory usage in recent applications has brought about a performance degradation problem due to hardware TLB misses. The capacity of the hardware TLB is limited because of the hardware cost, so the hardware TLB can cache only a small range of virtual addresses with the 4 KB page units. In order to improve the hardware TLB hit rate, the emulator considers use of a large page, with which a larger virtual memory area can be collectively mapped transparently to the guest (without any change on the guest). If a page unit is 4 KB (this page unit is also called a normal page), for example, a large page refers to a page which is larger than the normal page unit, and has a size of 1 MB, for example. However, a certain continuous virtual memory area in the guest cannot be simply mapped with a large page. This is because a guest OS (operating system) basically manages and protects its memory in normal page units.
Another case where a virtual memory area cannot be mapped with a large page is where normal pages in the large page have different memory protection attributes. A typical example is a case where pages having different memory protection attributes such as a readable and writable page and a read-only page exist on a single large page area. Another example is a case where a normal page mapped to a physical memory area and a normal page not mapped to a physical memory area exist on the same large page area. However, even in these cases, if the virtual memory area can be replaced with a large page, performance can be improved by reduced hardware TLB misses.
As a known method for reducing hardware TLB misses by use of a large page, there is a method (see “Practical, transparent operating system support for superpages” J. Navarro et al, OSDI, 2002, for example) in which an OS collectively promotes 4 KB pages having the same page attribute to a large page transparently to the application, and demotes the large page to the 4 KB pages when the attribute of any of the pages is changed. However, this method cannot detect nor forbidden an unauthorized read access or write access to a virtual memory area.
Additionally, there is a translation lookaside buffer (see Japanese Patent Application Publication No. Hei 8-101797, for example) as a TLB for translating a virtual address into a physical address for a virtual page having a variable page size, for example. The translation lookaside buffer described in Japanese Patent Application Publication No. Hei 8-101797 can reduce TLB misses by use of a victim cache, but does not deal with a case where there are multiple memory protection attributes.
Moreover, there is a remapping apparatus (see Japanese Patent Application Publication No. Hei 8-36528, for example) in which a virtual address is firstly translated into an intermediate address, and then the intermediate address is translated into a physical address, so that multiple discontinuous physical pages can be mapped to a larger virtual large page. However, the remapping apparatus disclosed in Japanese Patent Application Publication No. Hei 8-36528 requires a remapping lookaside buffer (RLB) in addition to a translation lookaside buffer (TLB) to perform address translation using an intermediate address. Hence, the cost for address translation is doubled, and system performance is degraded.
Furthermore, there is a program loading method (see Japanese Patent Application Publication No. 2006-260395, for example) used for loading a program to a virtual address space in which the page size of at least one area differs from the page size of another area. In this method, the frequency of TLB misses is lowered by assigning a text or the like of a program either to an area having the smallest page size among areas having a larger page size than the size of the text or the like of the program, or to an area having the largest page size among areas having a smaller page size than the size of the text or the like. However, in the program loading method described in Japanese Patent Application Publication No. 2006-260395, the page size is determined when loading the program, and thus the page size cannot be determined appropriately when a mapping from a virtual address to a physical address dynamically changes.